Stacked semiconductor package

摘要

Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

主权项

1. A stacked semiconductor package comprising:
a lower chip having a through electrode area in which a plurality of through electrodes are disposed, said through electrode area arranged along a direction that is transverse to a longitudinal direction of an active surface of the lower chip; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of bonding pads corresponding to the plurality of through electrodes are disposed; wherein:
the lower chip comprises a function block area arranged apart from the through electrode area;a plurality of function blocks are disposed in the function block area;the active surface of the lower chip has a first length measured in the longitudinal direction and a second length measured in a transverse direction;the first length is greater than the second length;the through electrode area extends in the transverse direction of the active surface of the lower chip and has a first width measured in the longitudinal direction; anda length of each edge of at least one of the plurality of function blocks is longer than or equal to half of a difference between the first length and the first width.