发明名称 |
Error corrected pre-read for upper page write in a multi-level cell memory |
摘要 |
Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data. |
申请公布号 |
US9543019(B2) |
申请公布日期 |
2017.01.10 |
申请号 |
US201213710913 |
申请日期 |
2012.12.11 |
申请人 |
Intel Corporation |
发明人 |
Frickey Robert E.;Wakchaure Yogesh B.;Chao Iwen;Guo Xin;Gaewsky Kristopher H. |
分类号 |
G06F11/10;G11C16/10;G11C11/56 |
主分类号 |
G06F11/10 |
代理机构 |
Alpine Technology Law Group LLC |
代理人 |
Alpine Technology Law Group LLC |
主权项 |
1. A controller-based method to program a multi-level cell (MLC) memory, comprising:
receiving, in a controller, a write command from a host device, the write command comprising a program address and program data; in response to the write command, mapping the program address to a targeted page of memory in the MLC memory; and determining, in the controller, whether the targeted page of memory comprises an upper page and a lower page, and in response to a determination that targeted page of memory comprises an upper page and a lower page:
reading the lower page of the targeted page of memory to obtain lower page data, wherein the MLC memory has been programmed with the lower page data;error correcting the lower page data to generate error corrected lower page data;allocating one or more new pages of memory in the MLC memory;calculating an error correcting code to be included with the error corrected lower page data;determining whether the MLC memory would have to decrease a voltage threshold to program the error corrected lower page data, and in response to a determination that the MLC memory would have to decrease a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the one or more new pages of memory in the MLC memory; andprogramming the MLC memory using the error corrected lower page data and the program data. |
地址 |
Santa Clara CA US |