Interconnect structure for E/O engines having impedance compensation at the integrated circuits' front end

摘要

The present invention relates to an interconnect structure for coupling at least one electronic unit for outputting and/or receiving electric signals, and at least one optical unit for converting said electric signals into optical signals and/or vice versa, to a further electronic component. The interconnect structure comprises an electrically insulating substrate (102) and a plurality of signal lead pairs (104, 120) to be coupled between said electronic unit (108, 116) and a front end contact region (106) for electrically contacting said interconnect structure by said further electronic component. A ground plane layer (118) is electrically insulated from said pairs of signal leads (104, 120), wherein each pair of signal leads (104, 120) has a circuit connecting region (122) for electrically contacting respective terminals of said at least one electronic unit (108, 116), and wherein in a region adjacent to said terminals of said at least one electronic unit (108, 116) said ground plane layer (118) has a plurality of clearances (126) that are each allocated to one pair of signal leads (104, 120) and separated from a respective neighboring clearance.

主权项

1. An interconnect structure for coupling at least one electronic unit for outputting and receiving electric signals relative to a further electronic component and at least one optical unit for at least one of converting said electric signals into optical signals and converting said optical signals into electric signals, said interconnect structure comprising:
an electrically insulating substrate and a plurality of signal lead pairs to be coupled between said at least one electronic unit and a frontend contact region for electrically contacting said interconnect structure by said further electronic component, said interconnect structure further comprising a ground plane layer which is electrically insulated from said plurality of signal lead pairs, wherein each pair of the plurality of signal lead pairs has a circuit connecting region for electrically contacting respective terminals of said at least one electronic unit, wherein in a region adjacent to said respective terminals of said at least one electronic unit said ground plane layer has a plurality of clearances that are each allocated to one pair of the plurality of signal lead pairs and separated from a respective neighbouring clearance, wherein a ground plane layer web separates at least two signal lead pairs.