Differential signal reversion and correction circuit and method thereof

摘要

A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

主权项

1. A differential signal reversion and correction circuit, comprising:
two interconnected nodes; and a data frame sending module and a reversion control signal generating module disposed between the two interconnected nodes, the data frame sending module, including:
a first input port, a second input port, a second output port, a third input port, and a third output port, the first input port is connected to a P line and an N line through a first buffer, the second input port, the second output port, the third input port, and the third output port are connected to each other in parallel and then are connected to the P line and the N line respectively; and the reversion control signal generating module, including:
a second buffer connected to the P line and the N line,a comparator connected in series to the second buffer, anda control link, the control link including an uplink and a downlink, wherein
the uplink is a first control switch, wherein an input of the first control switch is disposed at a configuring module which is positioned between the buffer and the comparator, the first control switch is connected in series to the configuring module, and an output of the first control switch is connected to the P line and the N line respectively, andthe downlink is a second control switch, wherein an input of the second control switch is disposed between the buffer and the comparator, and an output of the second control switch is connected to the P line and the N line respectively.