发明名称 Vertical memory devices and methods of manufacturing the same
摘要 A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.
申请公布号 US9543307(B2) 申请公布日期 2017.01.10
申请号 US201514792114 申请日期 2015.07.06
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Kim Ha-Na;Jang Dae-Hyun;Oh Jung-Ik
分类号 H01L21/02;H01L21/48;H01L27/105;H01L27/02 主分类号 H01L21/02
代理机构 Harness, Dickey & Pierce, PLC 代理人 Harness, Dickey & Pierce, PLC
主权项 1. A method of manufacturing a vertical memory device, the method comprising: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure on the cell array region of the substrate, the mold structure having a first portion and a second portion integrally connected to the first portion, the second portion having a plurality of steps; forming an insulating layer on the second portion of the mold structure; forming a common source line opening, the common source line opening extending through the first portion and the second portion of the mold structure in a first direction, the first direction being perpendicular to an upper surface of the substrate; forming cell gate line contact holes extending-through the insulating layer in the first direction to the plurality of steps, each step of the plurality of steps being exposed by at least one of the cell gate line contact holes; and simultaneously forming a first contact plug in the common source line opening and second contact plugs in the cell gate line contact holes, wherein an upper surface of the first contact plug is substantially coplanar with upper surfaces of the second contact plugs.
地址 Gyeonggi-Do KR