High density vertical nanowire stack for field effect transistor

摘要

An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.

主权项

1. A semiconductor structure comprising:
at least one semiconductor nanowire pair located over a substrate, wherein each of said at least one semiconductor nanowire pair includes:
a lower semiconductor nanowire having a vertical cross-sectional shape of an upright triangle; andan upper semiconductor nanowire having a vertical cross-sectional shape of an inverted triangle: a semiconductor material source structure having a rectangular vertical cross-sectional shape adjoined to said lower semiconductor nanowire and said upper semiconductor nanowire; a semiconductor material drain structure having another rectangular vertical cross-sectional shape adjoined to said lower semiconductor nanowire and said upper semiconductor nanowire; a source cap material portion located on said semiconductor material source structure; a drain cap material portion located on said semiconductor material drain structure, said source cap material portion is spaced apart from said drain cap material portion; a raised source region in direct physical contact with a sidewall surface of each of said semiconductor material source structure and said source cap material portion and extending onto a topmost surface of said source cap material portion; and a raised drain region in direct physical contact with a sidewall surface of each of said semiconductor material drain structure and said drain cap material portion and extending onto a topmost surface of said drain cap material portion.