Antifuse memory cells and arrays thereof

摘要

An antifuse memory cell includes an antifuse element and a gate PN diode. The antifuse element includes a gate terminal coupled to a word line, a drain terminal coupled to a bit line, and a body terminal. The gate PN diode is coupled between the word line and the gate terminal.

主权项

1. An antifuse memory cell comprising:
an active region extending in a first direction, and having a channel region of a first conductivity type, the active region be defined by a trench isolation layer; a first impurity junction region of a second conductivity type and the second impurity junction region of the second conductivity type, wherein the first and the second impurity junction regions are separated from each other by the channel region in an upper region of the active region; a gate electrode extending in a second direction to intersect the active region, and having a first gate electrode of the second conductivity type that overlaps with the channel region of the active region and a second gate electrode of the first conductivity type that is in contact with the first gate electrode along the second direction without overlapping with the active region; an insulation layer between the active region and the gate electrode, a first contact plug over the second gate electrode and coupled to a word line; and a second contact plug over the second impurity junction region and coupled to a bit line, wherein the first impurity junction region is electrically floated.