Strain release in PFET regions

摘要

A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

主权项

1. A method for fabricating a semiconductor device, comprising:
providing a strained silicon on insulator (SSOI) structure, wherein the SSOI structure comprises at least a substrate, a dielectric layer disposed on the substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer; forming a plurality of fins on the SSOI structure by etching the strained semiconductor material layer and the silicon germanium layer down to the dielectric layer, wherein at least one fin of the plurality of fins is in a nFET region of the SSOI structure and at least one fin of the plurality of fins is in a pFET region of the SSOI structure; forming a first gate structure over a first portion of the at least one fin of the plurality of fins in the nFET region; forming a second gate structure over a second portion of the at least one fin of the plurality of fins in the pFET region, such that the second gate structure surrounds the second portion on three sides; removing the second gate structure over the second portion of the at least one fin of the plurality of fins in the pFET region; removing the silicon germanium layer exposed by the removal of the second gate structure over the second portion, wherein the removal of the silicon germanium layer exposed by the removal of the second gate structure releases strain in the at least one fin of the plurality of fins in the pFET region; and forming a third gate structure over the second portion of the at least one fin of the plurality of fins in the pFET region, such that the third gate structure surrounds the second portion on all four sides.