Smart holding registers to enable multiple register accesses

摘要

A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.

主权项

1. A processor comprising:
target registers; N holding registers, wherein each of the N holding registers is associated with a source and is configured to refrain from pushing any subsets of an update received from the source to one of the target registers until all of the subsets of the update have been received from the source; and a bus coupling the target registers and the N holding registers, wherein when the bus is accessed by one of the holding registers, the bus includes a source identifier indicating the one of the N holding registers that the access is from.