Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

摘要

Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

主权项

1. A system for performing a static timing analysis, said system comprising:
a memory storing an integrated circuit design partitioned into multiple hierarchical entities; and, at least one processor accessing said memory and identifying multiple signal pathways within a hierarchical entity selected for analysis from said multiple hierarchical entities, said multiple signal pathways identified by said processor comprising at least a first signal pathway, and said at least one processor further performing the following: determining an internal timing constraint of a specific logic device in said first signal pathway based on a known reference value; deriving a first boundary timing constraint associated with said first signal pathway based on said internal timing constraint; deriving a second boundary timing constraint associated with said first signal pathway based on said first boundary timing constraint and a target slack value for said internal timing constraint, said first boundary timing constraint and said second boundary timing constraint are boundaries of valid timing signals for said hierarchical entity; performing a static timing analysis of said hierarchical entity using said second boundary timing constraint; making design adjustments to said hierarchical entity based on results of said static timing analysis; iteratively repeating said determining of said internal timing constraint, said deriving of said first boundary timing constraint, said deriving of said second boundary timing constraint, said performing of said static timing analysis, and said making of said design adjustments in order to minimize overlap between victim and aggressor timing windows prior to generating an overall signal timing model for said integrated circuit design; and generating a timing abstraction for said hierarchical entity based on said static timing analysis, multiple ones of said timing abstraction being used to generate said overall signal timing model for said integrated circuit design.