Synchronization of domain counters

摘要

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a master counter to store a time stamp count for the processor; a plurality of cores, each core including a core counter to store a time stamp count for the core; and synchronization logic to, in response to a de-synchronization event in a first core of the plurality of cores:
obtain a value of the master counter;initiate a first core counter using the value of the master counter, wherein the first core counter is included in the first core;compare a synchronization digit of the first core counter to a synchronization signal indicating only a value of a synchronization digit of the master counter, wherein the first core counter and the master counter each include only one synchronization digit; andin response to a determination that the synchronization digit of the first core counter does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal.