Multiplexer-memory cell circuit, layout thereof and method of manufacturing same

摘要

An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one adjacent logic tile, and wherein a first logic tile includes: (i) a plurality of static memory cells to store data, wherein each memory cell includes a first output, (ii) a multiplexer including inputs, an output and input selects, (iii) a plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell, (iv) poly-silicon extensions, each poly-silicon extension is (a) connected to an associated poly-silicon conductor and (b) coupled to an associated input select of the multiplexer, wherein the poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the first logic tile.

主权项

1. An integrated circuit disposed in and on a substrate, the integrated circuit comprising:
a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, is configurable to communicate, during operation, with at least one logic tile that is adjacent to an edge, and wherein a first logic tile of the plurality of logic tiles includes:
a plurality of memory cells to store data, wherein each memory cell includes a first output;a multiplexer including a plurality of inputs, an output and a plurality of input selects;a first plurality of poly-silicon conductors, each poly-silicon conductor is disposed in the substrate and connected to the first output of an associated memory cell; anda first plurality of poly-silicon extensions, each poly-silicon extension is (i) connected to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled to an associated input select of the multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor in the first logic tile.