| 发明名称 |
Systems and methods for processing data with power ramp control |
| 摘要 |
An apparatus for processing data includes a data processing circuit configured to process user data, wherein the data processing circuit comprises a number of sub-circuits, a number of clock gates each configured to control a clock signal to one of the sub-circuits, a gating control circuit configured to control the clock gates to apply the clock signal to each of the sub-circuits in staged fashion during a ramped power up operation, and a dummy data source configured to provide dummy data to the data processing circuit during the ramped power up operation of the data processing circuit. |
| 申请公布号 |
US9542982(B1) |
申请公布日期 |
2017.01.10 |
| 申请号 |
US201514965872 |
申请日期 |
2015.12.10 |
| 申请人 |
Avago Technologies General IP (Singapore) Pte. Ltd. |
发明人 |
Nguyen Kaitlyn T.;Yang Shaohua;Liu Dan;Yan Xiao Dong;Zuo Qi |
| 分类号 |
G11C7/00;G11C7/12;G11C8/10;G11C7/14;G11C5/14 |
主分类号 |
G11C7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus for processing data, comprising:
a data processing circuit configured to process user data, wherein the data processing circuit comprises a plurality of sub-circuits; a plurality of clock gates each configured to control a clock signal to one of the plurality of sub-circuits; a gating control circuit configured to control the plurality of clock gates to apply the clock signal to each of the plurality of sub-circuits in staged fashion during a ramped power up operation; and a dummy data source configured to provide dummy data to the data processing circuit during the ramped power up operation of the data processing circuit. |
| 地址 |
Singapore SG |
