Method of performing dynamic voltage and frequency scaling operation, application processor performing method, and mobile device comprising application processor

摘要

A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit.

主权项

1. A method of performing a dynamic voltage and frequency scaling operation, the method comprising:
controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor; and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit; when the operating frequency information indicates an increase of the operating frequency of the application processor, controlling the CMU to increase the operating frequency of the application processor after controlling the PMIC to increase the operating voltage of the application processor; and when the operating frequency information indicates a decrease of the operating frequency of the application processor, controlling the CMU to decrease the operating frequency of the application processor before controlling the PMIC to decrease the operating voltage of the application processor, wherein: the operating frequency of the application processor corresponds to a frequency of a clock signal that is output from a clock generating unit, and the frequency of the clock signal is determined by the CMU, the clock generating unit comprises multiple phase locked loops (PLLs), a multiplexer, and a frequency divider, and the frequency of the clock signal is determined such that an output frequency of one output signal selected by the multiplexer among multiple output signals output from the PLLs is divided by the frequency divider.