Testing architecture of circuits integrated on a wafer

摘要

An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

主权项

1. A wafer, comprising:
a first integrated-circuit die; a scribe line adjacent to the first integrated-circuit die; a testing circuit disposed in the scribe line; a first contact pad disposed in the first integrated-circuit die; a second contact pad disposed in the first integrated-circuit die; and a first switch element disposed in the first integrated-circuit die and having a first node coupled to the testing circuit and having a second node coupled to the first contact pad and having a control node directly connected to the second contact pad, wherein an open and closed state of the first switch for selectively connecting the testing circuit and the first contact pad is changeable during execution of a test solely in response to changing a control signal applied to the second contact pad.