Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor

摘要

A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

主权项

1. A computing system comprising:
an instruction dispatch module configured to:
receive a program instruction,generate a tag for the program instruction,allocate the tag in a program order in a tag module; and an address reordering module, coupled to the instruction dispatch module, configured to:
filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter, anddeallocate the tag from the tag module when the program instruction is repeated for prefetching.