发明名称 |
Interconnect routing configurations and associated techniques |
摘要 |
Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed. |
申请公布号 |
US9542522(B2) |
申请公布日期 |
2017.01.10 |
申请号 |
US201414491693 |
申请日期 |
2014.09.19 |
申请人 |
Intel Corporation |
发明人 |
Qian Zhiguo;Aygun Kemal;Kim Dae-Woo |
分类号 |
H01L23/48;H01L21/336;G06F17/50;H01L23/538;H01L23/00;H01L21/768 |
主分类号 |
H01L23/48 |
代理机构 |
Schwabe, Williamson & Wyatt, P.C. |
代理人 |
Schwabe, Williamson & Wyatt, P.C. |
主权项 |
1. An apparatus comprising:
a substrate; a first routing layer disposed on the substrate and having a first plurality of traces; and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces, and a third trace of the first plurality of traces has a width that is less than a width of a fourth trace of the second plurality of traces, and the first trace and the second traces are ground traces, and the third trace is a dummy trace, and the fourth trace is a signal trace. |
地址 |
Santa Clara CA US |