发明名称 3D Chip-On-Wafer-On-Substrate Structure With Via Last Process
摘要 Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
申请公布号 US2017005027(A1) 申请公布日期 2017.01.05
申请号 US201615264245 申请日期 2016.09.13
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Chen Ming-Fa;Tsai Wen-Ching
分类号 H01L23/48;H01L21/768;H01L21/311;H01L23/00;H01L23/498 主分类号 H01L23/48
代理机构 代理人
主权项 1. A package comprising: a first redistribution layer (RDL) disposed on a first semiconductor substrate; a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL; an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate; a first conductive element disposed in the first RDL; a via extending from a top surface of the insulating film, through the first semiconductor substrate to the first conductive element; and a first spacer disposed between the first semiconductor substrate and the via, wherein the first spacer extends through the first semiconductor substrate.
地址 Hsin-Chu TW