EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART

摘要

A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

主权项

1. A system comprising:
a plurality of processors; a processor interconnect to communicatively couple two or more of the plurality of processors; a system memory communicatively coupled to one or more of the plurality of processors over a memory interconnect; one of the plurality of processors comprising: a plurality of cores to execute instructions; a cache shared by two or more of the plurality of cores; one of the cores comprising:
an instruction memory to store instructions;a decoder to decode instructions;an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the core as a single instruction; andthe instruction fusion circuit to fuse the first and second instructions when both the first and second instructions have been stored in the instruction memory prior to issuance.