发明名称 DISPLAY SYSTEM, AN INTEGRATED CIRCUIT FOR USE IN THE DISPLAY SYSTEM, AND A METHOD OF DISPLAYING AT LEAST TWO IMAGES ON AT LEAST TWO SCREENS
摘要 A display system and a method of displaying a separate image on each one of at least two N-bit screens simultaneously, are hereby presented. The display system comprises at least two data processing units arranged for controlling the display of pixels on the corresponding N-bit screen, and a single merger block arranged for receiving pixel data from each respective data processing unit and for transmitting said pixel data to the corresponding N-bit screen. The merger block comprises a multiplexer unit arranged for selectively coupling one of the data processing units to an output of the merger block, a selection unit arranged for driving the multiplexer unit, and a clock generating unit adapted for generating at least one clock signal and for shifting the at least one generated clock signal compared to a main clock signal, the main clock signal and the generated clock signal being used to clock one of the N-bit screens, respectively.
申请公布号 US2017004791(A1) 申请公布日期 2017.01.05
申请号 US201514954283 申请日期 2015.11.30
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 AUBINEAU VINCENT;PERRET GUILLAUME;STAUDENMAIER MICHAEL ANDREAS
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
主权项 1. A display system comprising: a visual display unit with at least two N-bit screens; a display control unit with: at least two data processing units, each being associated with a corresponding N-bit screen and arranged for controlling the display of pixels on the corresponding N-bit screen; anda single merger block arranged for receiving pixel data from each of the data processing units and for outputting said pixel data to the associated N-bit screen, wherein the merger block comprises an input corresponding to each data processing unit and coupled to the corresponding data processing unit, and an output,a multiplexer unit arranged for selectively directing data from one of the data processing units received on a respective one of the inputs to the output of the merger block,a selection unit arranged for driving said multiplexer unit,a clock generating unit arranged for providing a separate clock signal for each of the N-bit screens, wherein one clock signal is a main clock signal, and each other clock signal is generated by shifting said main clock signal, said main clock signal and said other clock signal being used to clock a respective one of the N-bit screens, and wherein the display control unit is configured to cause the display of a separate image on each N-bit screen simultaneously.
地址 Austin TX US