| 摘要 |
According to one embodiment, a first Pixel is connected to a first source line via a first switch included in a first Pixel and the second Pixel is connected to a second source line via a second switch included in the second Pixel. The first Pixel has a first memory, and the second Pixel has a second memory. A first potential line supplies data 1 and a second potential line supplies data 0. The first and second Pixels can store data 1 or 0, when a gate signal is applied to a gate line and the first and second switches are turned on. In this case, in order to store the same data (1 or 0) in the first and second memories, the first and second source lines should be applied different revel signals each other. |
| 主权项 |
1. A display device comprising:
parallel gate lines; parallel source lines crossing the gate lines; a first potential line and a second potential line parallel to each of the gate lines for outputting data; and pixels arranged near intersections of the gate lines and the source lines, respectively, wherein each of the pixels comprises: a first switch, a corresponding source line being connected to an input electrode of the first switch, the first switch being turned on when a corresponding gate line is at one potential and turned off when the gate line is at other potential; a second switch, an input electrode of the second switch being connected to an output electrode of the first switch in series, the second switch being turned off when the corresponding gate line is at the one potential and turned on when the gate line is at the other potential; and a memory circuit which stores any one of first logical data of the first potential line and second logical data of the second potential line when the first switch is turned on and any one of a high level input signal and a low level input signal is input from the corresponding source line, and a logical data input terminal of a first memory circuit of a first pixel is connected to the first potential line and a logical data input terminal of a second memory circuit of a second pixel adjacent to the first pixel is connected to the second potential line, and the first and second memory circuits have same logic data when input signals of different levels are supplied to source lines corresponding to the first and second pixels while a first switch of each of the first and second pixels is in an on-state. |
