| 摘要 |
It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level γ. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power P m and a second signal having a power P a , a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value Θ, wherein -π < Θ < π. The amplifier arrangement further comprises a combining network. Circuit element values of the combining network, the power P m and the power P a , the phase offset value Θ, a bias condition of the auxiliary transistor; and a relative size S aux of the auxiliary transistor, are based on a predetermined back-off power level γ, a current scaling factor r c of the auxiliary transistor, a main transistor oversizing factor r o,m , and an auxiliary transistor oversizing factor r o,a , where r c < 1, r o,m ≥ 1 and r o,a ≥ 1. It is also provided a method for determining properties for an amplifier arrangement. |
