发明名称 BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION
摘要 Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word is facilitated between the master device and the slave device via a control data bus. The encoded communication is encoded according to a protocol that allocates a plurality of least significant bits of the encoded communication to facilitate maximizing an error detection constant. The protocol allocates the plurality of least significant bits to include at least one additional error detection bit or at least a first most significant bit of a data portion of the word.
申请公布号 EP3111561(A1) 申请公布日期 2017.01.04
申请号 EP20150711929 申请日期 2015.02.28
申请人 Qualcomm Incorporated 发明人 SENGOKU, Shoichiro
分类号 H03M13/09 主分类号 H03M13/09
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