发明名称 Trench power MOSFET and manufacturing method thereof
摘要 A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P+/N− or N+/P− junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P+/N− or N+/P− junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.
申请公布号 US9536972(B2) 申请公布日期 2017.01.03
申请号 US201514862754 申请日期 2015.09.23
申请人 SUPER GROUP SEMICONDUCTOR CO., LTD. 发明人 Hsu Hsiu-Wen
分类号 H01L29/78;H01L29/66;H01L29/423;H01L27/088;H01L21/8234;H01L29/10;H01L29/51;H01L29/08 主分类号 H01L29/78
代理机构 Li & Cai Intellectual Property (USA) Office 代理人 Li & Cai Intellectual Property (USA) Office
主权项 1. A trench power MOSFET comprising: a substrate; an epitaxial layer formed on the substrate; and a plurality of trench transistor units formed in the epitaxial layer, wherein each of the trench transistor units includes a trench gate structure, comprising: a trench formed in the epitaxial layer, wherein an insulating layer is formed on an inner wall of the trench; anda gate filled in the trench, wherein the gate includes an upper doped region, a lower doped region and a middle region interposed therebetween, wherein the upper doped region has a conductive type reverse to a conductive type of the lower doped region, and the middle region has a carrier concentration smaller than that of each of the upper and lower doped regions; a source region, formed in the epitaxial layer and adjacent to side walls of the trench gate structure; and a body region, formed in the epitaxial layer under the source region and adjacent to side walls of the trench gate structure.
地址 Hsinchu County TW