Semiconductor memory device including a 3-dimensional memory cell array and a method of operating the same

摘要

A semiconductor memory device may include a plurality of cell strings. Each of the cell strings may include at least one source selection transistor connected to a common source line, a plurality of memory cells connected to the common source line through the at least one source selection transistor. Each of the cell strings may include at least one source selection line connected to source selection transistors of the plurality of the cell strings. The semiconductor memory device may include peripheral circuit. The peripheral circuit may be configured to control the plurality of the cell strings. The peripheral circuit may be configured to perform a program on the source selection transistors connected to a selected source selection line by applying a program voltage to the selected source selection line among the at least one source selection line, and by applying a reference voltage to the common source line.

主权项

1. A semiconductor memory device comprising:
a plurality of cell strings, each of the plurality of the cell strings including a first source selection transistor connected to a common source line, memory cells connected to the common source line through the first source selection transistor and a drain selection transistor connected between the memory cells and a bit line; a first source selection line connected to the first source selection transistors included in the plurality of the cell strings; a plurality of word lines connected to the memory cells included in each of the plurality of cell strings, respectively; a drain selection line connected to the drain selection transistors included in the plurality of the cell strings; and a peripheral circuit configured to control the plurality of cell strings, wherein the peripheral circuit is configured to perform a program on the first source selection transistors connected to the first source selection line by applying a program voltage to the first source selection line, and by applying a turn-off voltage to the drain selection line to turn-off the drain selection transistors included in the plurality of the cell strings, or floating the drain selection line.