| 发明名称 |
Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor |
| 摘要 |
A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor. |
| 申请公布号 |
US9535488(B2) |
申请公布日期 |
2017.01.03 |
| 申请号 |
US201414281729 |
申请日期 |
2014.05.19 |
| 申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
Henry G. Glenn;Gaskins Stephan |
| 分类号 |
G06F13/00;G06F1/32;G06F12/08;G06F13/24;G06F9/44;G06F13/364;G06F9/38;G06F9/30;G06F1/04;G06F1/12 |
主分类号 |
G06F13/00 |
| 代理机构 |
|
代理人 |
Davis E. Alan;Huffman James W. |
| 主权项 |
1. A microprocessor, comprising:
an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions. |
| 地址 |
New Taipei TW |
