Adaptive dynamic keeper circuit

摘要

Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.

主权项

1. A dynamic circuit, comprising:
a logical state node; a keeper circuit coupled to the logical state node, the keeper circuit comprising a first circuit element configured to output a control signal that affects an activation delay associated with the keeper circuit; and a pull down circuit coupled to the logical state node, the pull down circuit comprising a second circuit element; wherein the first circuit element is configured to electrically float the control signal in parallel with the second circuit element changing a voltage on the logical state node during at least a portion of an evaluation phase of the dynamic circuit.