发明名称 |
Method and system of layout placement based on multilayer gridlines |
摘要 |
A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality. |
申请公布号 |
US9536032(B2) |
申请公布日期 |
2017.01.03 |
申请号 |
US201414554958 |
申请日期 |
2014.11.26 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Chiang Ting-Wei;Tien Li-Chun;Zhuang Hui-Zhong;Jiang Zhe-Wei |
分类号 |
G06F17/50;H03K19/02;H01L27/02 |
主分类号 |
G06F17/50 |
代理机构 |
Hauptman Ham, LLP |
代理人 |
Hauptman Ham, LLP |
主权项 |
1. A method of forming a layout design for fabricating an integrated circuit, the method comprising:
identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the region of the layout design being sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality, K being an integer equal to or greater than two, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch, wherein the line pattern includes a layout pattern aligned with a grid line of the first set of grid lines overlapping a layout pattern aligned with a grid line of the second set of grid lines; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns, k being an order index ranging from 1 to K, and at least one of the above operations being performed by a hardware processor. |
地址 |
TW |