发明名称 Phase-based packet prioritization
摘要 A network node comprises a receiver configured to receive a first packet, a processor coupled to the receiver and configured to process the first packet, and prioritize the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and a transmitter coupled to the processor and configured to transmit the first packet. An apparatus comprises a processor coupled to the memory and configured to generate instructions for a packet prioritization scheme, wherein the scheme assigns priority to packet transactions based on closeness to completion, and a memory coupled to the processor and configured to store the instructions. A method comprises receiving a first packet, processing the first packet, prioritizing the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and transmitting the first packet.
申请公布号 US9537799(B2) 申请公布日期 2017.01.03
申请号 US201313954210 申请日期 2013.07.30
申请人 Futurewei Technologies, Inc. 发明人 Lih Iulin;He Chenghong;Shi Hongbo;Zhang Naxin
分类号 H04L12/861;H04L12/833;H04L12/801 主分类号 H04L12/861
代理机构 Conley Rose, P.C. 代理人 Conley Rose, P.C.
主权项 1. A network node comprising: a central processing unit (CPU) configured to receive, from a first cache of the node, a first packet having m transaction phases and a second packet having n transaction phases, wherein m and n are different, and wherein the transaction phases of the first packet and the second packet are sequential steps related to processing and forwarding of the first packet and the second packet, wherein the CPU is configured to: process the first packet and the second packet;determine a total number of transaction phases in the first packet and the second packet; andassign priority to the first packet and the second packet based on the transaction phase of each packet, wherein a transaction phase closer to transaction completion has a higher priority over transaction phases closer to transaction initiation, wherein highest priority is assigned to packets in their last transaction phase, and wherein a last transaction phase of the first packet has the same priority as a last transaction phase of the second packet; and a transmitter coupled to the CPU and configured to transmit the first packet and the second packet to a second cache of the node according to the assigned priority in order to reduce latency of the first packet and the second packet.
地址 Plano TX US