发明名称 Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture
摘要 Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.
申请公布号 US9537503(B2) 申请公布日期 2017.01.03
申请号 US201615151042 申请日期 2016.05.10
申请人 MAXLINEAR, INC. 发明人 Chen Xuefeng;Chan Kok Lim;Fogleman Eric;Ye Sheng
分类号 H03M1/38;H03M1/06;H03M1/12;H03M1/46 主分类号 H03M1/38
代理机构 McAndrews, Held & Malloy, Ltd. 代理人 McAndrews, Held & Malloy, Ltd.
主权项 1. A system, comprising: a meta-stability detector that comprises: a timing control circuit that is operable to measure comparison time for each conversion cycle in an analog-to-digital convertor (ADC);a plurality of signal adjustment circuits, wherein each one of the plurality of signal adjustment circuits is operable to apply a logical operation to one or more input signals to the one of the plurality of signal adjustment circuits to provide a corresponding output signal; anda plurality of signal state circuits, wherein each one of the plurality of signal state circuits is operable to: store state information relating to one or more input signals to the one of the plurality of signal state circuits, for at least one processing cycle; andprovide an output signal based on prior stored information; wherein: the plurality of signal state circuits, the plurality of signal adjustment circuits, and the timing control circuit are arranged to generate one or more control signals for controlling at least some of operations or components in the ADC, during analog-to-digital conversions, based on one or more input signals generated or used within the ADC during analog-to-digital conversions.
地址 Carlsbad CA US