Transforming a phase-locked-loop generated chip clock signal to a local clock signal

摘要

Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.

主权项

1. A method for transforming a chip clock signal to a local clock signal, the method comprising:
generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, wherein the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; generating the local clock signal based on the second clock signal; and wherein the chip clock signal input and the second control signal input connect to inputs of a first logic gate, and an output of the first logic gate and the first control signal connect to inputs of a second logic gate.