Method to prevent oxide damage and residue contamination for memory device

摘要

The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

主权项

1. A method of forming an integrated circuit (IC), the method comprising:
patterning a first masking layer over a semiconductor substrate comprising a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region; forming a first plurality of dielectric bodies within the first plurality of openings and a second plurality of dielectric bodies within the second plurality of openings, wherein the first and second plurality of dielectric bodies extend into the semiconductor substrate; forming a second masking layer over the first masking layer and the first and second plurality of dielectric bodies; removing the first and second masking layers at the memory cell region; forming a first conductive layer having a first portion at the memory cell region filling recesses between the first plurality of dielectric bodies and a second portion out of the memory cell region extending over the second masking layer; and performing a planarization to reduce a height of the first portion and remove the second portion of the first conductive layer.