Serial/parallel control, separate tap, master reset synchronizer for tap domains

摘要

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

主权项

1. An integrated circuit, comprising:
(a) tap domain test access port circuitry having a test data in (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data out (TDO) output lead; and (b) serial to parallel control circuitry having a TMS/TDI input lead, a clock input lead, and a TDO output lead, the serial to parallel control circuitry being connected to the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry and to the TDO output lead of the serial to parallel control circuitry, the serial to parallel control circuitry including:
(i) serial input parallel output circuitry having a serial input connected to the TMS/TDI input lead, a clock input connected with the clock input lead, a TDI output, and a TMS output;(ii) update register circuitry having a first input connected to the TDI output of the serial input parallel output circuitry and a first output connected to the TDI output lead and having a second input connected to the TMS output of the serial input parallel output circuitry and a second output connected to the TMS output lead;(iii) tap state machine circuitry separate from the tap domain test access port circuitry, the tap state machine circuitry having a TCK input connected to the TCK output lead, a TMS input connected to the TMS output lead, and a reset output; and(iv) master reset and synchronizer circuitry having a clock input coupled to the clock input lead, a TMS/TDI input coupled to the a TMS/TDI input lead, a reset input coupled to the reset output, a master reset output, and a controller enable output.