Memory device and signal processing circuit

摘要

A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.

主权项

1. A semiconductor device comprising:
a first memory circuit comprising a first transistor and a first capacitor; a second memory circuit comprising a second transistor and a second capacitor; a logic circuit comprising first to fourth nodes; a first control circuit; a second control circuit; and a precharge circuit, wherein a first terminal of the first transistor is electrically connected to one electrode of the first capacitor, wherein a first terminal of the second transistor is electrically connected to one electrode of the second capacitor, wherein a second terminal of the first transistor is electrically connected to the first node, a first terminal of the first control circuit, a first terminal of the second control circuit, and a first terminal of the precharge circuit, wherein the second terminal of the first transistor is directly connected to the first terminal of the first control circuit, and the first terminal of the second control circuit, wherein a second terminal of the second transistor is electrically connected to the second node, a second terminal of the first control circuit, a second terminal of the second control circuit, and a second terminal of the precharge circuit, wherein the second terminal of the second transistor is directly connected to the second terminal of the first control circuit, and the second terminal of the second control circuit, wherein a third terminal of the first control circuit is electrically connected to the third node, and wherein a third terminal of the second control circuit is electrically connected to the fourth node.