Arithmetic processing device, method of controlling arithmetic processing device, and information processing device

摘要

An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit, and a second arithmetic processing unit including a second instruction controller and a second cache unit. The first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction, and in response to the invalidation request, the second cache unit determines whether a second transaction is to be aborted based on information in the invalidation request when the second transaction conflicts with the first transaction for a cache block corresponding to a destination of the write request, and sends a determination result to the first arithmetic processing unit.

主权项

1. An arithmetic processing device comprising:
a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit having a first cache memory; and a second arithmetic processing unit including a second instruction controller that controls a write instruction to the memory and a second cache unit having a second cache memory, wherein the first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction in execution by the first arithmetic processing unit the invalidation request including a destination address of the write request and a predetermined information, and in response to the invalidation request, the second cache unit of the second arithmetic processing unit makes a first determination as to whether the second transaction conflicts with the first transaction for a cache block corresponding to the destination address of the write request, and a second determination as to whether a second transaction in execution by the second arithmetic processing unit is to be aborted based on the predetermined information, determines to abort the second transaction when both of the first and second determinations are true, or not to abort the second transaction when either the first or second determination is false, and sends a determination result to the first arithmetic processing unit.