| 发明名称 | Interconnection of multiple chips in a package | ||
| 摘要 | An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. | ||
| 申请公布号 | US9535865(B2) | 申请公布日期 | 2017.01.03 |
| 申请号 | US201113996107 | 申请日期 | 2011.12.22 |
| 申请人 | Intel Corporation | 发明人 | Thomas Thomas P.;Osborne Randy B.;Kumar Rajesh |
| 分类号 | G06F13/00;G06F13/364;G06F13/14;G06F13/40;G06F13/42;G06F3/0488;G06F13/16 | 主分类号 | G06F13/00 |
| 代理机构 | Blakely, Sokoloff, Taylor & Zafman LLP | 代理人 | Blakely, Sokoloff, Taylor & Zafman LLP |
| 主权项 | 1. An apparatus comprising: a semiconductor chip package comprising: a) a first set of single-ended transmitter circuits on a first die having a master device wherein the single-ended transmitter circuits have no equalization;b) a first set of single-ended receiver circuits on a second die, wherein the receiver circuits have no termination and no equalization, the second die having a slave device responsive to the master device of the first die; andc) a plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched. | ||
| 地址 | Santa Clara CA US | ||