Crystal oscillation circuit, gain stage of crystal oscillation circuit and method for designing same

摘要

A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.

主权项

1. A gain stage of crystal oscillation circuit, comprising:
a substrate, having at least a first zone and a second zone; a first N doped region, disposed in the first zone; a plurality of first gates, disposed parallel on the first N doped region; a plurality of first P+ doped regions, disposed in the first N doped region; a plurality of second P+ doped regions, disposed in the first N doped region, wherein the first P+ doped regions serve as sources of a plurality of first transistors respectively, the first gates serve as gates of the first transistors respectively, and the second P+ doped regions serve as drains of the first transistors respectively; a first P doped region, disposed in the second zone, wherein the first P doped region is parallel to the first N doped region; a plurality of second gates, disposed parallel on the first P doped region; a plurality of first N+ doped regions, disposed in the first P doped region; a plurality of second N+ doped regions, disposed in the first P doped region, wherein the first N+ doped regions serve as sources of a plurality of second transistors respectively, the second gates serve as gates of the second transistors respectively, and the second N+ doped regions serve as drains of the second transistors respectively; and a plurality of metal wires, disposed parallel on the first N doped region and the first P doped region, wherein each of the metal wires is electrically coupled to the drain of at least one corresponding first transistor among the first transistors and the drain of at least one corresponding second transistor among the second transistors.