Method and algorithm for functional critical paths selection and critical path sensors and controller insertion

摘要

CAD software examines delays of paths in a design from design engineers and first selects the longest paths. Then all paths that converge with these longest paths are examined for delays, and a fastest converging path is selected for each of the longest paths. The longest paths are again sorted by the fastest converging delay, and paths with slower converging paths are selected to be Functional Critical Paths (FCP's). Functional critical path timing sensors are added to each FCP to test setup time with an added margin delay. When the margined path delays fail to meet setup requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. The CAD software can replicate some of the FCP's and add toggle pattern generators and timing sensors and a margin controller to adjust the margin delay.

主权项

1. An Integrated Circuit (IC) product produced by a process of:
generating path delays for a plurality of paths in an IC design specification; sorting the path delays and selecting a top M % of paths sorted by maximum path delay; examining the top M % of paths to locate converging paths; generating converging path delays for the converging paths; finding a minimum converging path delay for each of the top M % of paths; sorting the minimum converging paths delays and selecting a top N % of the top M % of paths having largest minimum converging path delays; identifying the top N % of the top M % of paths as Functional Critical Paths (FCP); adding a functional critical path timing sensor to an output of each FCP; adding a voltage controller that controls a local power-supply voltage to the plurality of paths and to the functional critical path timing sensors; connecting FCP timing-failure outputs of the functional critical path timing sensors to inputs of the voltage controller, wherein the voltage controller is for increasing the local power-supply voltage when a FCP timing-failure output is activated, and for decreasing the local power-supply voltage when no FCP timing-failure output has been activated for a period of time; writing images of the IC product to a plurality of photomasks, the images including images of the functional critical path timing sensors connected to identified FCP's; and using the plurality of photomasks to print the images onto a semiconductor substrate during steps in an IC manufacturing process to build a plurality of dice of the IC product onto the semiconductor substrate, whereby the IC product has added circuitry for sensing of timing-failures of selected paths to control the local power-supply voltage to compensate for timing failures.