Three dimensional logic circuit

摘要

A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.

主权项

1. An integrated circuit, comprising:
a multi-bit flip-flop circuit with a plurality of single bit flip-flop circuits, each single bit flip-flop circuit of the plurality of single bit flip-flop circuits comprises a clocked portion driven by a clock signal and a non-clocked portion; a common clock circuit, each of the clocked portions of the plurality of single bit flip-flop circuits being connected to the common clock circuit; a common scan circuit, each of the non-clocked portions of the plurality of single bit flip-flop circuits are connected to the common scan circuit; wherein the clocked portions of the plurality of single bit flip-flop circuits are in a first tier and each of the clocked portions comprises a master latch component, a slave latch component, and a plurality of transmission gates; and wherein the non-clocked portions of the plurality of single bit flip-flop circuits are in a second tier positioned above the first tier and each of the non-clocked portions comprises a data input, an inverted data input, a scan input, and a plurality of input/output transistors.