Cache control device and cache control method

摘要

A cache control device includes an area determination unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of an allocation ratio of an execution time per unit time, which is allocated to each of a plurality of the instruction flows by a CPU. The area determination unit specifies the area allocated to the specified instruction flow in response to an access request from a memory access unit, and accesses the specified area in the cache memory.

主权项

1. A cache control device, comprising:
an area determination unit comprising:
a processing unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of an allocation ratio of an execution time per unit time, for each of a plurality of the instruction flows by a processor, and generates area allocation information based on the determined area; andan allocation control unit that conducts a cache access based on the area allocation information, wherein the allocation ratio comprises slot allocation information defining a correspondence relationship between a plurality of time slots within the processor and the plurality of instruction flows, wherein the plurality of instruction flows includes a first instruction flow and a second instruction flow, wherein when a number of time slots allocated to the first instruction flow is larger than a number of time slots allocated to the second instruction flow, an area of the cache memory allocated to the first instruction flow is larger than an area of the cache memory allocated to the second instruction flow, wherein each of the plurality of instruction flows is allocated one or more time slots, wherein the cache memory includes a plurality of lines, each of which has an index value, and wherein the area determination unit uses slot number information of the time slots as the index value.