发明名称 Cache memory and cache memory control unit
摘要 Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
申请公布号 US9535841(B2) 申请公布日期 2017.01.03
申请号 US201013515315 申请日期 2010.12.14
申请人 SONY CORPORATION 发明人 Hirao Taichi;Sakaguchi Hiroaki;Yoshikawa Hiroshi;Ishii Masaaki
分类号 G06F13/00;G06F12/08 主分类号 G06F13/00
代理机构 Chip Law Group 代理人 Chip Law Group
主权项 1. A cache memory comprising: a tag storage section including a plurality of entries each including a tag address and a remaining number of times for reference, one or more entries being retrieved for reference through searching the plurality of entries by a first address segment which configures part of an access address, wherein each of the plurality of entries includes a field indicating whether or not data in a cache line of the corresponding entry and data in a main memory are identical to each other; a data storage section configured to store pieces of data each corresponding to the plurality of entries; circuitry configured to: compare a second address-segment which configures another part of the access address with the tag address included in each of the one or more of the retrieved entries, thereby to find an entry having a tag address that matches the second address-segment; and select a piece of data corresponding to the found entry from the data storage section, in a read access, wherein, in the read access, the circuitry is configured to invalidate the found entry without performing a write-back operation after the read access in a case that the remaining number of times for reference included in the found entry is equal to one, whereas the circuitry is configured to decrement, by one, the remaining number of times for reference included in the found entry in a case that the remaining number of times for reference is greater than one, and wherein, upon the invalidation of the found entry, the circuitry is configured to set a value of the field to “0”.
地址 Tokyo JP