Low-power source-synchronous signaling

摘要

A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

主权项

1. A method of operating a memory controller, the method comprising:
transmitting data signals to a memory device over each one of at least two parallel data links; sending a timing signal to the memory device on a first dedicated link, the timing signal having a fixed phase relationship with the data signals; driving a data strobe signal to the memory device on a second dedicated link; receiving phase information from the memory device, the phase information generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device to sample the data signals; and adjusting a phase of the data strobe signal relative to the timing signal based on the received phase information.