Photo pattern method to increase via etching rate

摘要

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

主权项

1. A semiconductor device comprising:
a conductive bottom substrate layer; an inter-metal dielectric layer disposed on the conductive bottom substrate layer, wherein the inter-metal dielectric layer defines a via with the conductive bottom substrate layer and surrounded by the inter-metal dielectric layer, wherein the via comprises a conductive via material in contact with a portion of the conductive bottom substrate layer; and a conductive top layer disposed on the inter-metal dielectric layer and the conductive via material, wherein the portion of the conductive bottom substrate layer in contact with the conductive via material is isolated from adjacent portions of the conductive bottom substrate layer, wherein the portion of the conductive bottom substrate layer in contact with the conductive via material is larger than the via, thereby providing an inter-metal dielectric boundary around the entire via above the portion of the conductive bottom substrate layer in contact with the conductive via material, and wherein the via has a via area mask open ratio of at least 90% to a via mask to define the via.