LATCH AND FREQUENCY DIVIDER

摘要

A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit includes a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit includes a second input terminal and a second output terminal; and a first feedforward control unit adapted for cutting off a first current path, wherein the first feedforward control unit includes a first clock signal input terminal adapted for receiving a first clock signal, a third output terminal coupled to the first output terminal, and at least two feedforward control terminals, at least one of which is coupled to the first input terminal or the second input terminal. Power consumption of the latch and the frequency divider can be reduced.

主权项

1. A latch, comprising:
a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit comprises a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit comprises a second input terminal and a second output terminal; and a first feedforward control unit adapted for cutting off a first current path between the power supply and the ground wire, wherein the first feedforward control unit comprises a first clock signal input terminal adapted for receiving a first clock signal, a third output terminal coupled to the first output terminal, and at least two feedforward control terminals, at least one of which is coupled to the first input terminal or the second input terminal.