SEMICONDUCTOR DEVICE

摘要

In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

主权项

1. A semiconductor device comprising:
a semiconductor substrate including an IGBT region and a diode region; and a front surface electrode provided on a front surface of the semiconductor substrate, wherein the IGBT region comprises: an n-type drift region; an n-type bather region provided on a front surface side of the drift region; a p-type body region provided on a front surface side of the barrier region; an n-type emitter region provided on a front surface side of the body region and configured to electrically connect to the front surface electrode; a p-type body contact region provided on the front surface side of the body region at a position different from a position of the emitter region, the p-type body contact region having an impurity concentration higher than an impurity concentration of the body region, and configured to electrically connect to the front surface electrode; a plurality of gate trenches extending from the front surface of the semiconductor substrate, piercing the emitter region, the body region and the bather region and reaching the drift region; and an n-type pillar region extending from the front surface of the semiconductor substrate between adjacent gate trenches, piercing the body region and reaching the barrier region, and configured to electrically connect to the front surface electrode and the barrier region; wherein the diode region comprises: an n-type drift region; an n-type barrier region provided on a front surface side of the drift region; a p-type anode region provided on a front surface side of the barrier region; a p-type anode contact region provided on at least a part of a front surface side of the anode region, the p-type anode contact region having the impurity concentration higher than an impurity concentration of the anode region, and configured to electrically connect to the front surface electrode; a plurality of gate trenches extending from the front surface of the semiconductor substrate, piercing at least the anode region and the barrier region and reaching the drift region; and an n-type pillar region extending from the front surface of the semiconductor substrate between adjacent gate trenches, piercing the anode contact region and the anode region and reaching the barrier region, and configured to electrically connect to the front surface electrode and the barrier region; wherein in a plan view of the semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region, and wherein in a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.