发明名称 クロック切替装置
摘要 PROBLEM TO BE SOLVED: To provide a clock switching device which can switch between two clock systems without interruption regardless of the clock select signal input timing.SOLUTION: In a clock switching device, a PLL is included which exerts oscillation frequency control based on a phase difference between an input signal based on an active system input clock and a feedback frequency-divided signal and thereby generates an oscillation clock. A phase difference period equivalent to a phase difference between a standby system input frequency-divided signal and the oscillation clock is detected, and assuming a point of time at which a duration equal to the phase difference period has elapsed after pre-system switchover frequency division of the oscillation clock started to be a post-system switchover start point, frequency division of the oscillation clock is started from that point of time to generate the feedback frequency-divided signal. Then, at a system switchover point, after reception of a select signal, which is determined depending on the phase difference period, system switchover is performed.
申请公布号 JP6036014(B2) 申请公布日期 2016.11.30
申请号 JP20120188633 申请日期 2012.08.29
申请人 沖電気工業株式会社 发明人 深沢 英一
分类号 H04L7/00;G06F1/04 主分类号 H04L7/00
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