发明名称 REDUCED MEMORY VECTORED DSL
摘要 A reduced-memory vectored DSL system reduces the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived. Memory is reduced in both the transmission of such FEXT data (between upstream and downstream ends) and within an upstream-end device such as a DSLAM that performs vectoring using a separate or internal vectoring processing apparatus.
申请公布号 EP2297912(A4) 申请公布日期 2016.11.30
申请号 EP20090774358 申请日期 2009.06.30
申请人 IKANOS COMMUNICATIONS, INC. 发明人 SANDS, NICHOLAS, P.;FISHER, KEVIN, D.
分类号 H04B3/32;H04B3/487;H04L1/00 主分类号 H04B3/32
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