| 摘要 |
A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data. |
| 主权项 |
1. A method of caching data in the memory of electronic processor units, comprising:
compiling, in a first electronic processor unit configured to perform data-parallel computations, a set of asymmetric coherent caching rules, wherein the set of rules configure the first electronic processor unit to be:
inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit,operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit, andoperable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data. |
