PROGRAMMING SELECT GATE TRANSISTORS AND MEMORY CELLS USING DYNAMIC VERIFY LEVEL

摘要

Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.