发明名称 スライスレベル調整を実施する方法、回路及びシステム
摘要 In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.
申请公布号 JP6024286(B2) 申请公布日期 2016.11.16
申请号 JP20120184923 申请日期 2012.08.24
申请人 富士通株式会社 发明人 マクロード・スコット;ネドヴィッチ・ニコラ
分类号 H04B10/69 主分类号 H04B10/69
代理机构 代理人
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